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? semiconductor components industries, llc, 2007 july, 2007 - rev. 1 1 publication order number: ncp5391/d ncp5391 2/3 phase buck controller for vr11 pentium iv processor applications the ncp5391 is a two- or three-phase buck controller which combines differential voltage and current sensing, and adaptive voltage positioning to power intel's most demanding pentium ? iv processors and low voltage, high current power supplies. dual-edge pulse-width modulation (pwm) combined with inductor current sensing reduces system cost by providing the fastest initial response to transient loads thereby requiring less bulk and ceramic output capacitors to satisfy transient load-line requirements. a high performance operational error amplifier is provided, which allows easy compensation of the system. the proprietary method of dynamic reference injection (patented) makes the error amplifier compensation virtually independent of the system response to vid changes, eliminating the need for tradeoffs between load transients and dynamic vid performance. features ? meets intel's vr 11.0 specification ? dual-edge pwm for fastest initial response to transient loading ? high performance operational error amplifier ? supports vr11 soft-start mode ? dynamic reference injection (patent# 7057381) ? 8-bit dac per intel's vr11 specifications ? dac range from 0.5 v to 1.6 v ? 0.5% system voltage accuracy ? 2 or 3-phase operation ? true differential remote voltage sensing amplifier ? phase-to-phase current balancing ? lossless differential inductor current sensing ? differential current sense amplifiers for each phase ? adaptive voltage positioning (avp) ? fixed no-load voltage positioning at C19 mv ? frequency range: 100 khz C 1.0 mhz ? threshold sensitive enable pin for vtt sensing ? power good output with internal delays ? programmable soft-start time ? operates from 12 v ? this is a pb-free device* applications ? pentium iv processors ? vrm modules ? graphics cards ? low voltage, high current power supplies device package shipping ? ordering information NCP5391MNR2G qfn32 (pb-free) 3000 / t ape & reel marking diagram ncp5391 = specific device code a = assembly location wl = wafer lot yy = year ww = work week = pb-free package ncp5391 awlyyww 1 http://onsemi.com ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd801 1/d. *for additional information on our pb-free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. *pin 33 is the thermal pad on the bottom of the device. qfn32, 5x5 mn suffix case 488am 32 1
ncp5391 http://onsemi.com 2 cs1n g1 drvon cs3 cs3n cs2 cs2n cs1 rosc2 vr_rdy vcc dgnd g3 1 vid0 2 vid1 3 vid2 4 vid3 5 vid4 6 vid5 7 vid6 8 vid7 ss 9 en 10 11 vs+ 12 vs- 13 diffout 14 comp 15 vfb vdrp ncp5391 2/3-phase buck controller (32-pin qfn) pin connections 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 16 g2 rosc ilim agnd down-bonded to exposed flag
ncp5391 http://onsemi.com 3 figure 1. simplified block diagram + - - + - + - + - + - + - + - + - + - + oscillator rosc cs1 cs1n cs2 cs2n cs3 cs3n ilim en vcc agnd uvlo vdrp g1 g2 g3 dgnd drvon vr_rdy current limit droop amplifier 9.0 v 1.3 v diffout 1.3 v comp vfb vs- vs+ diffout 1.3 v error amp diff amp fault vid7 vid6 vid4 vid3 vid2 vid1 vid0 vid5 ss vr11 dac dac ncp5391 gain = 6 gain = 6 gain = 6 fault over 4off enb enb enb + - fault logic 3 phase detect and monitor circuits rosc2
ncp5391 http://onsemi.com 4 vid0 vcc vid1 vid2 vid3 vid4 vid5 vid6 vid7 en vr_rdy vs- vs+ dgnd agnd vid0 vid1 vid2 vid3 vid4 vid5 vid6 vid7 vr_rdy vr_en vtt 680 pullups u1 rvcc cvcc1 +12 v vcc bst drvh sw drvl pgnd od in c1 c3 c4 12 v_filter l1 r2 c2 rs1 cs1 cs1 cs1n 12 v_filter ncp3418b vcc bst drvh sw drvl pgnd od in 12 v_filter 12 v_filter vcc bst drvh sw drvl pgnd od in 12 v_filter 12 v_filter ntd60n02rt4 cs2 cs2n cs3 cs3n drvon ss rosc comp + diffout rt2 riso2 cfb1 rfb1 rfb vfb rdrp vdrp cd1 rd1 ilim cf rf ch css rlim1 rlim2 vccp vssp ntd85n02rt4 cpu gnd ncp5391 rt2 located near output inductors d1 bat54ht1 g1 g2 g3 riso1 figure 2. 3-phase application schematic rosc2 rosc2 cosc2
ncp5391 http://onsemi.com 5 vid0 vcc vid1 vid2 vid3 vid4 vid5 vid6 vid7 en vr_rdy vs- vs+ dgnd agnd vid0 vid1 vid2 vid3 vid4 vid5 vid6 vid7 vr_rdy vr_en vtt 680 pullups u1 rvcc cvcc1 +12 v vcc bst drvh sw drvl pgnd od in c1 c3 c4 12 v_filter l1 r2 c2 rs1 cs1 cs1 cs1n 12 v_filter ncp3418b vcc bst drvh sw drvl pgnd od in 12 v_filter 12 v_filter ntd60n02rt4 cs2 cs2n cs3 cs3n drvon ss rosc comp + diffout rt2 riso2 cfb1 rfb1 rfb vfb rdrp vdrp cd1 rd1 ilim cf rf ch css rlim1 rlim2 vccp vssp ntd85n02rt4 cpu gnd ncp5391 rt2 located near output inductors d1 bat54ht1 g1 g2 g3 riso1 figure 3. 2-phase application schematic rosc2 rosc2 cosc2
ncp5391 http://onsemi.com 6 pin descriptions pin no. symbol description 1 - 8 vid0Cvid7 voltage id dac inputs. 9 en pull this pin high to enable controller. pull this pin low to disable controller . either an open-collector output (with a pull-up resistor) or a logic gate (cmos or totem-pole output) may be used to drive this pin. a low to high transition on this pin will initiate a soft start. if the enable function is not required, this pin should be tied directly to vref. 10 ss a capacitor from this pin to ground programs the soft-start time. 11 vs+ non-inverting input to the internal differential remote v core sense amplifier. 12 vs- inverting input to the internal differential remote v core sense amplifier. 13 diffout output of the differential remote sense amplifier. 14 comp output of the error amplifier. 15 vfb error amplifier inverting input. connect a resistor from this pin to diffout. the value of this resistor and the amount of current from the droop resistor (r drp ) will set the amount of output voltage droop (avp) during load. 16 vdrp current signal output for adaptive voltage positioning (avp). the voltage of this pin minus 1.3 v is proportional to the output current. connect a resistor from this pin to v fb to set the amount of avp current into the feedback resistor (r fb ) to produce an output voltage droop. leave this pin open for no avp. 17, 19, 21 csxn inverting input to current sense amplifier #x, x = 1, 2, 3 18, 20, 22 csx non-inverting input to current sense amplifier #x, x = 1, 2, 3 23 drvon gate driver enable output. this pin produces a logic high to enable gate drivers and a logic low to disable gate drivers and has an internal 70 k to ground. 24, 25, 26 g1 C g3 pwm control signal outputs to gate drivers. 27 dgnd power supply return for the digital circuits. connect to agnd. 28 vcc power for the internal control circuits. 29 vr_rdy voltage regulator ready (powergood) output. open drain type output with internal delays that will transition high when v core is higher than 300 mv below dac, low when v core is lower than 380 mv below dac, and low when v core is higher than dac+185 mv. this output is latched low if v core exceeds dac+185 mv until v cc is removed. 30 rosc2 use for enhanced performance 31 rosc a resistance from this pin to ground programs the oscillator frequency. also, this pin supplies a regulated 2.0 v which may be used with a voltage divider to the ilim pin to set the over current shutdown threshold as shown in the applications schematics. 32 ilim over current shutdown threshold. to program the shutdown threshold, connect this pin to the r osc pin via a resistor divider as shown in the applications schematics. to disable the over current feature connect this pin directly to the r osc pin. to guarantee correct operation, this pin should only be connected to the voltage generated by the r osc pin C do not connect this pin to any externally generated voltages. 33 thpad/ agnd copper pad on the bottom of the ic for heatsinking. this pin should be connected to the ground plane under the ic. power supply return for the analog circuits that control output voltage.
ncp5391 http://onsemi.com 7 maximum ratings rating value unit operating ambient temperature range 0 to 70 c operating junction temperature range 0 to 85 c storage temperature range -55 to 150 c lead temperature soldering, reflow (60 to 120 seconds minimum above 237 c) 260 c thermal resistance, junction-to-ambient (r ja ) on a thermally conductive pcb in free air 56 c/w jedec moisture sensitivity level 1 msl maximum voltage C vcc pin with respect to agnd 15 v maximum voltage C all other pins with respect to agnd 5.5 v minimum v oltage C all pins with respect to agnd -0.3 v maximum current into pins: comp, vdrp, diffout 3.0 ma maximum current into pins: vr_rdy, g1, g2, g3, ss, drvon 20 ma maximum current out of pins: comp, vdrp, diffout, rosc 3.0 ma maximum current out of pins: g1, g2, g3 20 ma stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. note: esd sen sitive device
ncp5391 http://onsemi.com 8 electrical characteristics (0 c < t a < 70 c; 0 c < t j < 85 c; 10.8 v < v cc < 13.2 v; all dac codes; c vcc = 0.1 f, f sw = 400 khz, unless otherwise stated) parameter test conditions min typ max unit error amplifier input bias current -200 -50 -10 na inverting input v oltage 1.0 k between vfb and comp pins - 1.3 - v input offset voltage (note 1) -1.0 - 1.0 mv open loop dc gain (note 1) c l = 60 pf to gnd, r l = 10 k to gnd - 78 - db open loop unity gain bandwidth (note 1) c l = 60 pf to gnd, r l = 10 k to gnd - 15 - mhz open loop phase margin (note 1) c l = 60 pf to gnd, r l = 10 k to gnd - 65 - slew rate (note 1) v in = 100 mv, g = -1.0 v/v, 1.2 v < v out < 2.2 v, c l = 60 pf, dc load = 125 a - 5.0 - v/ s maximum output v oltage i source = 1.0 ma 3.0 3.3 - v minimum output v oltage i sink = 1.0 ma - 0.9 1.0 v output source current (note 1) v out = 3.0 v - 2.0 - ma output sink current (note 1) v out = 1.0 v - 2.0 - ma remote sense differential amplifier vs+ input resistance (note 1) drvon = high drvon = low - - 17 0.5 - - k vs+ input open circuit v oltage (note 1) drvon = high drvon = low - - 0.67 0.05 - - v vs- input resistance (note 1) vs+ = dac voltage drvon = high - 10 - k vs- input open circuit voltage (note 1) drvon = high vs+ = dac voltage = 0.333* dac + 0.433 v input voltage range -0.3 - 3.0 v input offset voltage (note 1) -1.0 - 1.0 mv -3db bandwidth (note 1) c l = 80 pf to gnd, r l = 10 k to gnd - 12 - mhz dc gain i diffout = 100 a 0.982 1.0 1.018 v/v slew rate (note 1) v in = 1.0 v, v out = 1.0 v to 2.0 v, c l = 80 pf to gnd, load = 125 a - 10 - v/ s maximum output v oltage i source = 1.0 ma 3.0 - - v minimum output v oltage i sink = 1.0 ma - - 0.5 v output source current (note 1) v out = 2.1 v - 25 - ma output sink current (note 1) v out = 1.0 v - 1.4 - ma v drp adaptive voltage positioning amplifier current sense input to v drp gain -60 mv < (csx-csxn) < +60 mv, t a = 25 c 5.7 6.0 6.3 v/v current sense input to v drp output -3db bandwidth (note 1) c l = 330 pf to gnd, r l = 10 k to gnd - 7.2 - mhz 1. guaranteed by design. not tested in production.
ncp5391 http://onsemi.com 9 electrical characteristics (0 c < t a < 70 c; 0 c < t j < 85 c; 10.8 v < v cc < 13.2 v; all dac codes; c vcc = 0.1 f, f sw = 400 khz, unless otherwise stated) parameter unit max typ min test conditions v drp adaptive voltage positioning amplifier current sense input to v drp output slew rate (note 1) v(csx-csxn) = 25 mv (all phases), 1.3 v < v out < 1.9 v, c l = 330 pf to gnd, load = 400 a - 3.7 - v/ s current summing amp output of fset voltage csx C csxn = 0, csx =1.0 v -15 - +15 mv maximum v drp output voltage csx - csxn = 0.12 v (all phases), i source = 1.0 ma 3.02 - - v minimum v drp output voltage csx - csxn = -0.12 v (all phases), i sink = 1.0 ma - - 0.5 v output source current (note 1) vdrp = 2.9 v - 9.0 - ma output sink current (note 1) vdrp = 1.0 v - 2.0 - ma current sense amplifiers input bias current csx = csxn = 1.4 v -200 -50 -10 na common mode input voltage range (note 1) -0.3 - 2.0 v differential mode input voltage range -120 - 120 mv input offset voltage (note 1) csx = csxn = 1.0 v -3.0 - 3.0 mv current sense input to pwm comparator input gain 0 mv < (csx-csxn) < 25 mv t a = 25 c 5.7 6.0 6.3 v/v oscillator switching frequency range (note 1) 100 - 1000 khz switching frequency accuracy (note 1) r osc = 100 k , 2-phase 93.6 104 114.4 khz switching frequency accuracy r osc = 49.9 k , 2-phase 184.5 205 225.5 khz switching frequency accuracy r osc = 24.9 k , 2-phase 360 400 440 khz switching frequency accuracy r osc = 10 k , 2-phase 829 921 1013 khz switching frequency accuracy (note 1) r osc = 100 k , 3-phase 90 100 110 khz switching frequency accuracy r osc = 49.9 k , 3-phase 178.2 198 217.8 khz switching frequency accuracy r osc = 24.9 k , 3-phase 351 390 429 khz switching frequency accuracy r osc = 10 k , 3-phase 818 909 1000 khz r osc output voltage 10 k < r osc < 49.9 k 1.92 2.00 2.08 v r osc output voltage (note 1) 49.9 k < r osc < 100 k - 2.00 - v modulators (pwm comparators) minimum pulse width fs = 400 khz - 30 40 ns magnitude of the pwm ramp - 1.0 - v 0% duty cycle comp voltage when the pwm outputs remain lo - 1.2 - v 100% duty cycle comp voltage when the pwm outputs remain hi - 2.3 - v minimum pwm linear duty cycle (note 1) f s = 400 khz - 90 - % 1. guaranteed by design. not tested in production.
ncp5391 http://onsemi.com 10 electrical characteristics (0 c < t a < 70 c; 0 c < t j < 85 c; 10.8 v < v cc < 13.2 v; all dac codes; c vcc = 0.1 f, f sw = 400 khz, unless otherwise stated) parameter unit max typ min test conditions modulators (pwm comparators) pwm comparator offset mismatch (note 1) between any 2 phases, f s = 400 khz - - 40 mv phase angle error between adjacent phases, f s = 400 khz -15 - 15 propagation delay (note 1) ramp/comp crossing to gx high - 20 - ns propagation delay (note 1) ramp/comp crossing to gx low - 20 - ns pwm outputs output high v oltage sourcing 500 a 3.3 4.0 4.7 v output low voltage sinking 500 a - 25 100 mv rise time c l = 20 pf, vo = 0.3 to 2.0 v - 10 - ns fall time c l = 20 pf, vo = vmax to 0.7 v - 10 - ns output impedance C lo state resistance to gnd (gx = lo) - 50 - g3 gate pin source current during phase detect - 70 - a phase detection period - 50 - s g3 phase detect threshold resistance - - 1.0 k gate driver enable (drvon) output high v oltage sourcing 500 a 4.0 5.3 5.5 v output low voltage sinking 500 a - 50 200 mv rise time c l (pcb) = 20 pf, vo = 10% to 90% - 25 - ns fall time c l (pcb) = 20 pf, vo = 10% to 90% - 25 - ns internal pulldown resistance v cc < uvlo threshold - 70 140 k vr_rdy (power good) output saturation v oltage i sink = 10 ma - - 0.4 v rise time external pullup of 1.0 k to 1.25 v, c load = 20 pf, vo = 10% to 90% - - 150 ns output v oltage at power-up (note 1) external vr_rdy pullup resistor of 2.0 k to 5.0 v, t r_vcc 3 x t r_5v , 100 s t r_vcc 20 ms - - 1.0 v high C output leakage current vr_rdy = 5.5 v via 1.0 k - - 1.0 a upper threshold v oltage vcore increasing, dac = 1.3 v - 300 - mv below dac rising delay vcore increasing 0.3 1.40 2.0 ms falling delay vcore decreasing - 5.0 - s soft-st art ss pin source current enable = hi, v ss pin < 1.1 v - 5.0 - a ss pin source current enable = hi, v ss pin > 1.15 v, vr11 ss mode only 125 - - a soft-start ramp time c ss = 0.01 f, drvon = hi to v ss pin = 1.1 v 1.5 2.2 3.0 ms ss pin discharge voltage enable = lo - - 50 mv 1. guaranteed by design. not tested in production.
ncp5391 http://onsemi.com 11 electrical characteristics (0 c < t a < 70 c; 0 c < t j < 85 c; 10.8 v < v cc < 13.2 v; all dac codes; c vcc = 0.1 f, f sw = 400 khz, unless otherwise stated) parameter unit max typ min test conditions soft-st art soft-start discharge time from enable = lo to v ss pin < max discharge voltage, c ss = 0.01 f - 5.0 - s vr11 v boot threshold voltage - 1.081 - v vr11 dwell time at v boot (note 1) 50 225 900 s enable input enable high input leakage current en = 3.0 v - - 10 a upper threshold v upper 0.80 0.85 0.90 v lower threshold v lower 0.67 0.75 0.83 v total hysteresis v upper C v lower 70 100 130 mv enable delay time enable transitioning hi to start of ss voltage rise 0.5 1.5 3.0 ms disable delay time enable transitioning low to drvon = low - - 200 ns current limit current sense inputs to i lim gain (note 1) 20 mv < (csx-csxn) < 60 mv t a = 25 c (all cs channels together) 5.7 6.0 6.3 v/v ilim pin input bias current v ilim = 2.0 v - 0.1 1.0 a ilim pin working voltage range (note 1) 0.3 - 2.0 v ilim input offset voltage (note 1) -50 - 50 mv overvoltage protection overvoltage threshold (note 1) dac +160 dac+18 0 dac +200 mv undervoltage protection uvlo start threshold 8.2 9.0 9.5 v uvlo stop threshold 7.2 8.0 8.5 v uvlo hysteresis - 1.0 - v vid inputs upper threshold v upper - - 800 mv lower threshold v lower 400 - - mv input bias current v vidx = 1.25 v - 100 500 na delay before latching vid change (vid de-skewing) measured from the 1 st edge of a vid change 400 - 1000 ns internal dac slew rate limiter positive slew rate limit vid step range of +10mv to +500mv - 7.3 - mv/ s negative slew rate limit vid step range of -10mv to -500mv - 7.3 - mv/ s input supply current v cc operating current f sw = 400 khz - 20 - ma vr 11 dac system voltage accuracy 1.0 v < dac < 1.6 v 0.8 v < dac < 1.0 v 0.5 v < dac < 0.8 v - - 0.5 5.0 8.0 % mv mv no-load of fset v oltage from nominal dac specification with cs input vin = 0 v -19 mv 1. guaranteed by design. not tested in production.
ncp5391 http://onsemi.com 12 table 2: vr11 vid codes vid7 800 mv vid6 400 mv vid5 200 mv vid4 100 mv vid3 50 mv vid2 25 mv vid1 12.5 mv vid0 6.25 mv nominal dac voltage (v) hex 0 0 0 0 0 0 0 0 off 00 0 0 0 0 0 0 0 1 off 01 0 0 0 0 0 0 1 0 1.60000 02 0 0 0 0 0 0 1 1 1.59375 03 0 0 0 0 0 1 0 0 1.58750 04 0 0 0 0 0 1 0 1 1.58125 05 0 0 0 0 0 1 1 0 1.57500 06 0 0 0 0 0 1 1 1 1.56875 07 0 0 0 0 1 0 0 0 1.56250 08 0 0 0 0 1 0 0 1 1.55625 09 0 0 0 0 1 0 1 0 1.55000 0a 0 0 0 0 1 0 1 1 1.54375 0b 0 0 0 0 1 1 0 0 1.53750 0c 0 0 0 0 1 1 0 1 1.53125 0d 0 0 0 0 1 1 1 0 1.52500 0e 0 0 0 0 1 1 1 1 1.51875 0f 0 0 0 1 0 0 0 0 1.51250 10 0 0 0 1 0 0 0 1 1.50625 11 0 0 0 1 0 0 1 0 1.50000 12 0 0 0 1 0 0 1 1 1.49375 13 0 0 0 1 0 1 0 0 1.48750 14 0 0 0 1 0 1 0 1 1.48125 15 0 0 0 1 0 1 1 0 1.47500 16 0 0 0 1 0 1 1 1 1.46875 17 0 0 0 1 1 0 0 0 1.46250 18 0 0 0 1 1 0 0 1 1.45625 19 0 0 0 1 1 0 1 0 1.45000 1a 0 0 0 1 1 0 1 1 1.44375 1b 0 0 0 1 1 1 0 0 1.43750 1c 0 0 0 1 1 1 0 1 1.43125 1d 0 0 0 1 1 1 1 0 1.42500 1e 0 0 0 1 1 1 1 1 1.41875 1f 0 0 1 0 0 0 0 0 1.41250 20 0 0 1 0 0 0 0 1 1.40625 21 0 0 1 0 0 0 1 0 1.40000 22 0 0 1 0 0 0 1 1 1.39375 23 0 0 1 0 0 1 0 0 1.38750 24 0 0 1 0 0 1 0 1 1.38125 25 0 0 1 0 0 1 1 0 1.37500 26 0 0 1 0 0 1 1 1 1.36875 27 0 0 1 0 1 0 0 0 1.36250 28 0 0 1 0 1 0 0 1 1.35625 29 0 0 1 0 1 0 1 0 1.35000 2a 0 0 1 0 1 0 1 1 1.34375 2b 0 0 1 0 1 1 0 0 1.33750 2c 0 0 1 0 1 1 0 1 1.33125 2d
ncp5391 http://onsemi.com 13 table 2: vr11 vid codes vid7 800 mv hex nominal dac voltage (v) vid0 6.25 mv vid1 12.5 mv vid2 25 mv vid3 50 mv vid4 100 mv vid5 200 mv vid6 400 mv 0 0 1 0 1 1 1 0 1.32500 2e 0 0 1 0 1 1 1 1 1.31875 2f 0 0 1 1 0 0 0 0 1.31250 30 0 0 1 1 0 0 0 1 1.30625 31 0 0 1 1 0 0 1 0 1.30000 32 0 0 1 1 0 0 1 1 1.29375 33 0 0 1 1 0 1 0 0 1.28750 34 0 0 1 1 0 1 0 1 1.28125 35 0 0 1 1 0 1 1 0 1.27500 36 0 0 1 1 0 1 1 1 1.26875 37 0 0 1 1 1 0 0 0 1.26250 38 0 0 1 1 1 0 0 1 1.25625 39 0 0 1 1 1 0 1 0 1.25000 3a 0 0 1 1 1 0 1 1 1.24375 3b 0 0 1 1 1 1 0 0 1.23750 3c 0 0 1 1 1 1 0 1 1.23125 3d 0 0 1 1 1 1 1 0 1.22500 3e 0 0 1 1 1 1 1 1 1.21875 3f 0 1 0 0 0 0 0 0 1.21250 40 0 1 0 0 0 0 0 1 1.20625 41 0 1 0 0 0 0 1 0 1.20000 42 0 1 0 0 0 0 1 1 1.19375 43 0 1 0 0 0 1 0 0 1.18750 44 0 1 0 0 0 1 0 1 1.18125 45 0 1 0 0 0 1 1 0 1.17500 46 0 1 0 0 0 1 1 1 1.16875 47 0 1 0 0 1 0 0 0 1.16250 48 0 1 0 0 1 0 0 1 1.15625 49 0 1 0 0 1 0 1 0 1.15000 4a 0 1 0 0 1 0 1 1 1.14375 4b 0 1 0 0 1 1 0 0 1.13750 4c 0 1 0 0 1 1 0 1 1.13125 4d 0 1 0 0 1 1 1 0 1.12500 4e 0 1 0 0 1 1 1 1 1.11875 4f 0 1 0 1 0 0 0 0 1.11250 50 0 1 0 1 0 0 0 1 1.10625 51 0 1 0 1 0 0 1 0 1.10000 52 0 1 0 1 0 0 1 1 1.09375 53 0 1 0 1 0 1 0 0 1.08750 54 0 1 0 1 0 1 0 1 1.08125 55 0 1 0 1 0 1 1 0 1.07500 56 0 1 0 1 0 1 1 1 1.06875 57 0 1 0 1 1 0 0 0 1.06250 58 0 1 0 1 1 0 0 1 1.05625 59 0 1 0 1 1 0 1 0 1.05000 5a 0 1 0 1 1 0 1 1 1.04375 5b
ncp5391 http://onsemi.com 14 table 2: vr11 vid codes vid7 800 mv hex nominal dac voltage (v) vid0 6.25 mv vid1 12.5 mv vid2 25 mv vid3 50 mv vid4 100 mv vid5 200 mv vid6 400 mv 0 1 0 1 1 1 0 0 1.03750 5c 0 1 0 1 1 1 0 1 1.03125 5d 0 1 0 1 1 1 1 0 1.02500 5e 0 1 0 1 1 1 1 1 1.01875 5f 0 1 1 0 0 0 0 0 1.01250 60 0 1 1 0 0 0 0 1 1.00625 61 0 1 1 0 0 0 1 0 1.00000 62 0 1 1 0 0 0 1 1 0.99375 63 0 1 1 0 0 1 0 0 0.98750 64 0 1 1 0 0 1 0 1 0.98125 65 0 1 1 0 0 1 1 0 0.97500 66 0 1 1 0 0 1 1 1 0.96875 67 0 1 1 0 1 0 0 0 0.96250 68 0 1 1 0 1 0 0 1 0.95625 69 0 1 1 0 1 0 1 0 0.95000 6a 0 1 1 0 1 0 1 1 0.94375 6b 0 1 1 0 1 1 0 0 0.93750 6c 0 1 1 0 1 1 0 1 0.93125 6d 0 1 1 0 1 1 1 0 0.92500 6e 0 1 1 0 1 1 1 1 0.91875 6f 0 1 1 1 0 0 0 0 0.91250 70 0 1 1 1 0 0 0 1 0.90625 71 0 1 1 1 0 0 1 0 0.90000 72 0 1 1 1 0 0 1 1 0.89375 73 0 1 1 1 0 1 0 0 0.88750 74 0 1 1 1 0 1 0 1 0.88125 75 0 1 1 1 0 1 1 0 0.87500 76 0 1 1 1 0 1 1 1 0.86875 77 0 1 1 1 1 0 0 0 0.86250 78 0 1 1 1 1 0 0 1 0.85625 79 0 1 1 1 1 0 1 0 0.85000 7a 0 1 1 1 1 0 1 1 0.84375 7b 0 1 1 1 1 1 0 0 0.83750 7c 0 1 1 1 1 1 0 1 0.83125 7d 0 1 1 1 1 1 1 0 0.82500 7e 0 1 1 1 1 1 1 1 0.81875 7f 1 0 0 0 0 0 0 0 0.81250 80 1 0 0 0 0 0 0 1 0.80625 81 1 0 0 0 0 0 1 0 0.80000 82 1 0 0 0 0 0 1 1 0.79375 83 1 0 0 0 0 1 0 0 0.78750 84 1 0 0 0 0 1 0 1 0.78125 85 1 0 0 0 0 1 1 0 0.77500 86 1 0 0 0 0 1 1 1 0.76875 87 1 0 0 0 1 0 0 0 0.76250 88 1 0 0 0 1 0 0 1 0.75625 89
ncp5391 http://onsemi.com 15 table 2: vr11 vid codes vid7 800 mv hex nominal dac voltage (v) vid0 6.25 mv vid1 12.5 mv vid2 25 mv vid3 50 mv vid4 100 mv vid5 200 mv vid6 400 mv 1 0 0 0 1 0 1 0 0.75000 8a 1 0 0 0 1 0 1 1 0.74375 8b 1 0 0 0 1 1 0 0 0.73750 8c 1 0 0 0 1 1 0 1 0.73125 8d 1 0 0 0 1 1 1 0 0.72500 8e 1 0 0 0 1 1 1 1 0.71875 8f 1 0 0 1 0 0 0 0 0.71250 90 1 0 0 1 0 0 0 1 0.70625 91 1 0 0 1 0 0 1 0 0.70000 92 1 0 0 1 0 0 1 1 0.69375 93 1 0 0 1 0 1 0 0 0.68750 94 1 0 0 1 0 1 0 1 0.68125 95 1 0 0 1 0 1 1 0 0.67500 96 1 0 0 1 0 1 1 1 0.66875 97 1 0 0 1 1 0 0 0 0.66250 98 1 0 0 1 1 0 0 1 0.65625 99 1 0 0 1 1 0 1 0 0.65000 9a 1 0 0 1 1 0 1 1 0.64375 9b 1 0 0 1 1 1 0 0 0.63750 9c 1 0 0 1 1 1 0 1 0.63125 9d 1 0 0 1 1 1 1 0 0.62500 9e 1 0 0 1 1 1 1 1 0.61875 9f 1 0 1 0 0 0 0 0 0.61250 a0 1 0 1 0 0 0 0 1 0.60625 a1 1 0 1 0 0 0 1 0 0.60000 a2 1 0 1 0 0 0 1 1 0.59375 a3 1 0 1 0 0 1 0 0 0.58750 a4 1 0 1 0 0 1 0 1 0.58125 a5 1 0 1 0 0 1 1 0 0.57500 a6 1 0 1 0 0 1 1 1 0.56875 a7 1 0 1 0 1 0 0 0 0.56250 a8 1 0 1 0 1 0 0 1 0.55625 a9 1 0 1 0 1 0 1 0 0.55000 aa 1 0 1 0 1 0 1 1 0.54375 ab 1 0 1 0 1 1 0 0 0.53750 ac 1 0 1 0 1 1 0 1 0.53125 ad 1 0 1 0 1 1 1 0 0.52500 ae 1 0 1 0 1 1 1 1 0.51875 af 1 0 1 1 0 0 0 0 0.51250 b0 1 0 1 1 0 0 0 1 0.50625 b1 1 0 1 1 0 0 1 0 0.50000 b2 1 1 1 1 1 1 1 0 off fe 1 1 1 1 1 1 1 1 off ff off b3 to fd
ncp5391 http://onsemi.com 16 typical characteristics t a , ambient temperature ( c) 13.6 13.4 12.6 12.8 13.2 0 13.0 10 20 30 40 i cc , ic quiescent current (ma) 50 60 70 figure 4. ic quiescent current vs. ambient temperature figure 5. vcc undervoltage lockout threshold voltage vs. ambient temperature figure 6. typical dac voltage offset vs. temperature 10 9 7 8 v cc , undervoltage lockout threshold voltage (v) 10 t a , ambient temperature ( c) 0 20 3040506070 v cc increasing voltage v cc decreasing voltage 0.0188 0.0186 0.0182 0.0184 dac offset 0.0180 0.6 vid 0.5 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 70 c 0.0198 0.0196 0.0192 0.0194 0.0190 1.5 1.6 25 c 0 c
ncp5391 http://onsemi.com 17 functional description general the ncp5391 dual edge modulated multiphase pwm controller is specifically designed with the necessary features for a high current vr11 cpu power system. the ic consists of the following blocks: precision programmable dac, differential remote voltage sense amplifier, high performance voltage error amplifier, differential current feedback amplifiers, precision oscillator and triangle wave generators, and pwm comparators. protection features include undervoltage lockout, soft-start, overcurrent protection, overvoltage protection, and power good monitor. remote output sensing amplifier (rsa) a true differential amplifier allows the ncp5391 to measure vcore voltage feedback with respect to the vcore ground reference point by connecting the vcore reference point to vs+, and the vcore ground reference point to vs-. this configuration keeps ground potential differences between the local controller ground and the vcore ground reference point from af fecting regulation of vcore between vcore and vcore ground reference points. the rsa also subtracts the dac (minus vid offset) voltage, thereby producing an unamplified output error voltage at the diffout pin. this output also has a 1.3 v bias voltage to allow both positive and negative error voltages. precision dac a precision programmable dac is provided. this dac has 0.5% accuracy over the entire operating temperature range of the part. high performance voltage error amplifier the error amplifier is designed to provide high slew rate and bandwidth. although not required when operating as a voltage regulator, a capacitor from comp to vfb is required for stable unity gain test configurations. gate driver outputs and 2/3 phase operation the part can be configured to run in 2- or 3-phase mode. in 2-phase mode, phases 1 and 3 should be used to drive the external gate drivers as shown in the 2-phase applications schematic. in 2-phase mode, gate output g2 must be grounded as shown in the 2-phase applications schematic. the following truth table summarizes the modes of operation: mode gate output connections g1 g2 g3 2-phase normal gnd normal 3-phase normal normal normal these are the only allowable connection schemes to program the modes of operation. differential c urrent sense amplifiers three differential amplifiers are provided to sense the output current of each phase. the inputs of each current sense amplifier must be connected across the current sensing element of the phase controlled by the corresponding gate output (g1, g2 or g3). if 2 phase is unused, the differential inputs to that phase's current sense amplifier m ust be shorted together and connected to v ccp as shown in the 2-phase application schematics . a voltage is generated across the current sense element (such as an inductor or sense resistor) by the current flowing in that phase. the output of the current sense amplifiers are used to control three functions. first, the output controls the adaptive voltage positioning, where the output voltage is actively controlled according to the output current. in this function, all of the current sense outputs are summed so that the total output current is used for output voltage positioning. second, the output signal is fed to the current limit circuit. this again is the summed current of all phases in operation. finally, the individual phase current is connected to the pwm comparator. in this way current balance is accomplished. oscillator and t riangle wave generator a programmable precision oscillator is provided. the oscillator 's frequency is programmed by the resistance connected from the rosc pin to ground. the user will usually form this resistance from two resistors in order to create a voltage divider that uses the rosc output voltage as the reference for creating the current limit setpoint voltage. the oscillator frequency range is 100 khz/phase to 1.0 mhz/phase. the oscillator generates up to 3 triangle waveforms (symmetrical rising and falling slopes) between 1.3 v and 2.3 v. the triangle waves have a phase delay between them such that for 2-, 3-phase operation the pwm outputs are separated by 180 and 120 angular degrees, respectively.
ncp5391 http://onsemi.com 18 pwm comparators with hysteresis three pwm comparators receive the error amplifier output signal at their noninverting input. each comparator receives one of the triangle waves offset by 1.3 v at it's inverting input. the output of the comparator generates the pwm outputs g1, g2 and g3. during steady state operation, the duty cycle will center on the valley of the triangle waveform, with steady state duty cycle calculated by v out /v in . during a transient event, both high and low comparator output transitions shift phase to the points where the error amplifier output intersects the down and up ramp of the triangle wave. protection features undervoltage lockout an undervoltage lockout (uvlo) senses the vcc input. during powerup, the input voltage to the controller is monitored, and the pwm outputs and the soft-start circuit are disabled until the input voltage exceeds the threshold voltage of the uvlo comparator. the uvlo comparator incorporates hysteresis to avoid chattering, since vcc is likely to decrease as soon as the converter initiates soft-start. overcurrent shutdown a programmable overcurrent function is incorporated within the ic. a comparator and latch makeup this function. the inverting input of the comparator is connected to the ilim pin. the voltage at this pin sets the maximum output current the converter can produce. the rosc pin provides a convenient and accurate reference voltage from which a resistor divider can create the overcurrent setpoint voltage. although not actually disabled, tying the ilim pin directly to the rosc pin sets the limit above useful levels C effectively disabling overcurrent shutdown. the comparator noninverting input is the summed current information from the current sense amplifiers. the overcurrent latch is set when the current information exceeds the voltage at the ilim pin. the outputs are immediately disabled, the vr_rdy and drvon pins are pulled low, and the soft-start is pulled low. the outputs will remain disabled until the v cc voltage is removed and re-applied, or the enable input is brought low and then high. overvoltage protec tion and power good monitor an output voltage monitor is incorporated. during normal operation, if the voltage at the diffout pin exceeds 1.3 v, the vr_rdy pin goes low, the drvon signal remains high, the pwm outputs are set low. the outputs will remain disabled until the v cc voltage is removed and reapplied. during normal operation, if the output voltage falls more than 300 mv below the dac setting, the vr_rdy pin will be set low until the output rises. soft-start the ncp5391 incorporates an externally programmable soft-start. the soft-start circuit works by controlling the ramp-up of the dac voltage during powerup. the initial soft-start pin voltage is 0 v. the soft-start circuitry clamps the dac input of the remote sense amplifier to the ss pin voltage until the ss pin voltage exceeds the dac setting minus vid of fset. the soft-start pin is pulled to 0 v if there is an overcurrent shutdown, if the enable pin is low, if v cc is below the uvlo threshold, or if an overvoltage condition exists. the ncp5391 ramps vcore to 1.1 v at the ss capacitor charge rate, pauses at 1.1 v for 170 s, reads the vid pins to determine the dac setting, then ramps vcore to the final dac setting at the dynamic vid slew rate of 7.3 mv/ s. typical soft- start sequence is shown in the following graph. 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 voltage 0 time vid setting vcore v oltage ss pin voltage boot dwell time ncp5391 internal dynamic vid rate limit boot v oltage figure 7. typical vr11 soft-start sequence to vcore = 1.3 v
ncp5391 http://onsemi.com 19 application information the ncp5391 is a high performance multiphase controller optimized to meet the intel vr11 specifications. the demo board for the ncp5391 is available by request. it is configured as a three phase solution with decoupling designed to provide a 1.0 m load line under a 50 a step load. a schematic is available upon request from on semiconductor. startup procedure the demo board comes with a socket 775 and requires an intel dynamic load tool (vtt tool) available through a third party supplier, cascade systems. the web page is http://www.cascadesystems.net/. start by installing the test tool software. it' s best to power the test tool from a separate atx power supply. the test tool should be set to a valid vid code of 0.5 v or above in-order for the controller to start. consult the vtt help manual for more detailed instructions. startup sequence 1. make sure the vtt software is installed. 2. powerup the pc or laptop do not start the vtt software. 3. insert the vtt test tool adapter into the socket and lock it down. 4. insert the socket saver pin field into the bottom of the vtt test tool. 5. carefully line up the tool with the socket in the board and press tool into the board. 6. connect the scope probe, or dmm to the voltage sense lines on the test tool. when using a scope probe it is best to isolate the scope from the ac ground. make the ground connection on the scope probe as short as possible. 7. connect the first atx supply to the vtt tool. 8. powerup the first atx supply to the vtt tool. 9. start the vtt tool software in vr11 mode with the current limit set to 150 a. 10. using the vtt tool software, select a vid code that is 0.5 v or above. 11. connect the second atx supply to the demo board. 12. set the vid dip switches. all the vid switches should be up or open. 13. set the vr_enable dip switch down or closed. 14. start the second atx supply by turning it on and setting the pson dip switch low. the green vid lights should light up to match the vtt tool vid setting. 15. set the vr_enable dip switch up to start the ncp5391. 16. check that the output voltage is about 19 mv below the vid setting. step load testing the vtt tool is used to generate the high di/dt step load. select the dynamic loading option in the vtt test tool software. set the desired step load size, frequency, duty, and slew rate. see figures 8 and 9. figure 8. typical step load response v out load current figure 9. typical load release event v out load current
ncp5391 http://onsemi.com 20 dynamic vid testing the vtt tool provides for vid stepping based on the intel requirements. select the dynamic vid option. before enabling the test set the lowest vid to 0.5 v or greater and set the highest vid to a value that is greater than the lowest vid selection, then enable the test. see figures 10 through 12. figure 10. 1.6 to 0.5 dynamic vid response figure 11. dynamic vid settling time rising figure 12. dynamic vid settling time falling design methodology decoupling the v cc pin on the ic an rc input filter is required as shown in the v cc pin to minimize supply noise on the ic. the resistor should be sized such that it does not generate a large voltage drop between the 12 v supply and the ic. see the schematic values. understanding soft-start the controller will ramp to the 1.1 v, with a pause to capture the vid code then resume ramping to target value based on an internal slew rate limit. see figure 13. the controller is designed to regulate to the voltage on the ss pin until it reaches the internal dac voltage. the soft-start cap sets the initial ramp rate using a typical 5.0 a current. the typical value to use for the soft-start cap (ss), is typically set to 0.01 f. this results in a ramp time to 1.1 v of 2.2 ms based on equation 1. c ss i ss dt ss dv ss (eq. 1) 1.1v 2.2ms dv ss dt ss and i ss 5 a c ss 0.01 f figure 13. vr11 startup
ncp5391 http://onsemi.com 21 programming the current limit and the oscillator frequency the demo board is set for an operating frequency of approximately 300 khz. the osc pin provides a 2.0 v reference voltage which is divided down with a resistor divider and fed into the current limit pin ilim. calculate the total series resistance to set the frequency and then calculate the individual values for current limit divider. the series resistors rlim1 and rlim2 sink current to ground. this current is internally mirrored into a capacitor to create an oscillator. the period is proportional to the resistance and frequency is inversely proportional to the resistance. the resistance may be estimated by equation 2. this equation is valid for the individual phase frequency in both three and four phase mode. rosc 10.14 10 9 frequency 1440 (eq. 2) 32.36k 10.14 10 9 300k 1440 2 phase mode rosc 9.711 10 9 frequency 1111 (eq. 3) 3 phase mode figure 14. r osc vs. 2-phase mode f osc (khz) r osc (k ) 0 10 20 30 40 50 60 70 80 90 100 0 200 400 600 800 1000 f osc (2, calculated) f osc (2, measured) 0 10 20 30 40 50 60 70 80 90 100 0 200 400 600 800 1000 f osc (2, measured) 0 10 20 30 40 50 60 70 80 90 100 0 200 400 600 800 1000 f osc (3, measured) f osc (3, calculated) figure 15. r osc vs. 3-phase mode f osc (khz) r osc (k ) the current limit function is based on the total sensed current of all phases multiplied by a gain of 5.94. dcr sensed inductor current is function of the winding temperature. the best approach is to set the maximum current limit based on the expected average maximum temperature of the inductor windings. dcr tmax dcr 25c (eq. 4) (1 0.00393c -1 (t tmax - 25c)) calculate the current limit voltage: v ilimit 5.94 i min_ocp dcr tmax dcr 50c vout 2vinf s vin- vout l (n- 1) vout l 0.02 (eq. 5) solve for the individual resistors: (eq. 6) rlim2 v ilimit r osc 2v rlim1 r osc -r lim2 final equation for the current limit threshold i limit (t inductor ) 2vrlim2 rlim1 rlim2 0.02 5.94(dcr 25c (1 0.00393c -1 (t inductor - 25c))) vout 2vinf s vin- vout l (n- 1) vout l (eq. 7) the inductors on the demo board have a dcr at 25 c of 0.75 m . selecting the closest available values of 16.9 k for rlim1 and 15.8 k for rlim2 yield a nominal operating frequency of 305 khz and an approximate current limit of 180 a at 100 c. the total sensed current can be observed as a scaled voltage at the vdrp pin added to a positive, no-load offset of approximately 1.3 v. inductor selection when using inductor current sensing it is recommended that the inductor does not saturate by more than 10% at maximum load. the inductor also must not go into hard saturation before current limit trips. the demo board includes a four phase output filter using the t50- 8 core from micrometals with 4turns and a dcr target of 0.75 m @ 25 c. smaller dcr values can be used, however, current sharing accuracy and droop accuracy decrease as dcr decreases. use the excel spreadsheet for regulation accuracy calculations for a specific value of dcr.
ncp5391 http://onsemi.com 22 inductor current sense compensation the ncp5391 uses the inductor current sensing method. this method uses an rc filter to cancel out the inductance of the inductor and recover the voltage that is the result of the current flowing through the inductor's dcr. this is done by matching the rc time constant of the current sense filter to the l/dcr time constant. the first cut approach is to use a 0.47 f capacitor for c and then solve for r. rsense(t) l 0.47 fdcr 25c (1 0.00393c -1 (t- 25c)) (eq. 8) figure 16. the demoboard inductor measured 350 nh and 0.75 m at room temp. the act ual value used for rsense was 953 which matches the equation for rsense at approximately 50c. because the inductor value is a function of load and inductor temperature final selection of r is best done experimentally on the bench by monitoring the vdroop pin and performing a step load test on the actual solution. it is desirable to keep the rsense resistor value below 1.0 k whenever possible by increasing the capacitor values in the inductor compensation network. the bias current flowing out of the current sense pins is approximately 100 na. this current flows through the current sense resistor and creates an offset at the capacitor which will appear as a load current at the vdroop pin. a 1.0 k resistor will keep this offset at the droop pin below 2.5 mv. simple average pspice model a simple state average model shown in figure 17 can be used to determine a stable solution and provide insight into the control system. figure 17. + - + - - + vramp_min 1.3 v + - e e1 gain = 6 0 vin 12 0 12 0 l 12 (250e-9/3) dcr (0.85e-3/3) voff rdrp 5.11 k ch 22 p rf 4.3 k cf 1.5 n + - 1e3 r6 1 k unity gain bw = 15 mhz c3 10.6 n 0 voffset - + - + 0 - + 0 + - vdac 1.25 v cfb1 rfb1 680 p 100 rfb 1 k rbrd 0.75 m lbrd 12 100 p cbulk (560e-6*10) esrbulk (7e-3/10) eslbulk (3.5e-9/10) 2 1 + - i2 td = 10u tf = 50n pw = 40u per = 80u i1 = 10 i2 = 110 tr = 50n + - 1aac 0adc esrcer (1.5e-3/18) eslcer (1.5e-9/18) 1 ccer (22e-6*18) 2 0 3 voff 1.3 vout
ncp5391 http://onsemi.com 23 a complex switching model is available by request which includes a more detailed board parasitic for this demo board. compensation and output filter design the values shown on the demo board are a good place to start for any similar output filter solution. the dynamic performance can then be adjusted by swapping out various individual components. if the required output filter and switching frequency are significantly different, it's best to use the available pspice models to design the compensation and output filter from scratch. the design target for this demo board was 1.0 m out to 2.0 mhz. the phase switching frequency is currently set to 300 khz. it can easily be seen that the board impedance of 0.75 m between the load and the bulk capacitance has a large effect on the output filter. in this case the ten 560 f bulk capacitors have an esr of 7.0 m . thus the bulk esr plus the board impedance is 0.7 m + 0.75 m or 1.45 m . the actual output filter impedance does not drop to 1.0 m until the ceramic breaks in at over 375 khz. the controller must provide some loop gain slightly less than one out to a frequency in excess 300 khz. at frequencies below where the bulk capacitance esr breaks with the bulk capacitance, the dc-dc converter must have sufficiently high gain to control the output impedance completely. standard type-3 compensation works well with the ncp5391. rfb1 should be kept above 50 for amplifier stability reasons. the goal is to compensate the system such that the resulting gain generates constant output impedance from dc up to the frequency where the ceramic takes over holding the impedance below 1.0 m . see the example of the locations of the poles and zeros that were set to optimize the model above. -100 -80 -60 -40 -20 0 20 40 60 80 100 1000 10000 100000 1000000 10000000 frequency db zout open loop zout closed loop open loop gain with current loop closed voltage loop compensation gain rf/rfb rf/rfb1 1/(2*pi*cf*rf) 1/(2*pi*(rbrd+esrbulk)*cbulk) 1/(2*pi*sqrt(esl_cer*ccer)) 1mohm 1/(2*pi*ccer*(rbrd+esrbulk)) 1/(2*pi*cfb1*(rfb1+rfb)) error amp open loop gain 1/(2*pi*rf*ch) figure 18. by matching the following equations a good set of starting compensation values can be found for a typical mixed bulk and ceramic capacitor type output filter. 1 2 cfrf 1 2 (rbrd esrbulk)cbulk (eq. 9) 1 2 cfbi(rfbi rfb) 1 2 ccer * (rbrd esrbulk)
ncp5391 http://onsemi.com 24 rfb is always set to 1.0 k and rfb1 is usually set to 100 for maximum phase boost. the value of rf is typically set to 4.0 k . droop injection and thermal compensation the vdrp signal is generated by summing the sensed output currents for each phase and applying a gain of approximately six. vdrp is externally summed into the feedback network by the resistor rdrp. this induces an offset which is proportional to the output current thereby forcing the controlled resistive output impedance. rrdp determines the target output impedance by the basic equation: (eq. 10) vout iout zout rfbdcr5.94 rdrp rdrp rfbdcr5.94 zout the value of the inductor's dcr varies with temperature according to the following equation 10: dcr tmax dcr 25c (1 0.00393c -1 (t tmax - 25c)) (eq. 11) the system can be thermally compensated to cancel this effect out to a great degree by adding an ntc (negative temperature coefficient resistor) in parallel with rfb to reduce the droop gain as the temperature increases. the ntc device is nonlinear. putting a resistor in series with the ntc helps make the device appear more linear with temperature. the series resistor is split and inserted on both sides of the ntc to reduce noise injection into the feedback loop. the recommended value for riso1 and riso2 is approximately 1.0 k . the output impedance varies with inductor temperature by the equation: zout(t) rfbdcr 25c (1 0.00393c -1 (t max - 25c))5.94 rdroop (eq. 12) by including the ntc rt2 and the series isolation resistors the new equation becomes: zout(t) rfb(riso1 rt2(t) riso2) rfb riso1 rt2(t) riso2 dcr 25c (1 0.00393c -1 (t max - 25c))5.94 rdroop (eq. 13) the typical equation of a ntc is based on a curve fit equation 13. (eq. 14) rt2(t) rt2 25c e
1 273 t 1 298 the demo board is populated with a 10 k ntc with a beta of 4300. figure 19 shows the uncompensated and compensated output impedance versus temperature. figure 19. uncompensated and compensated output impedance vs. temperature on semiconductor provides an excel spreadsheet to help with the selection of the ntc. the actual selection of the ntc will be effected by the location of the output inductor with respect to the ntc and airflow, and should be verified with an actual system thermal solution. ovp the overvoltage protection threshold is not adjustable. ovp protection is enabled as soon as soft-start begins and is disabled w hen the part is disabled. when ovp is tripped, the controller commands all four gate drivers to enable their low side mosfets, and vr_rdy transitions low. the ovp is non-latching and auto recovers. the ovp circuit monitors the output of diffout. if the diffout signal reaches 180 mv above the nominal 1.3 v offset the ovp will trip. the diffout signal is the difference between the output voltage and the dac voltage plus the 1.3 v internal offset. this results in the ovp tracking the dac voltage even during a dynamic change in the vid setting during operation. gate driver and mosfet selection on semiconductor provides the companion gate driver ic (ncp3418b). the ncp3418b driver is optimized to work with a range of mosfets commonly used in cpu applications. the ncp3418b provides special functionality and is required for the high performance dynamic vid operation of the part. contact your local on semiconductor applications engineer for mosfet recommendations. board stack-up the demo board follows the recommended intel stack-up and copper thickness as shown.
ncp5391 http://onsemi.com 25 figure 20. board layout a complete allegro atx and btx demo board layout file and schematics are available by request at www.onsemi.com and can be viewed using the allegro free physical viewer 15.x from the cadence website http://www.cadence.com/. close attention should be paid to the routing of the sense traces and control lines that propagate away from the controller ic. routing should follow the demo board example. for further information or layout review contact on semiconductor.
ncp5391 http://onsemi.com 26 package dimensions qfn32 5x5, 0.5p case 488am-01 issue o seating 32 x k 0.15 c (a3) a a1 d2 b 1 9 16 17 32 2 x 2 x e2 32 x 8 24 32 x l 32 x bottom view exposed pad top view side view d a b e 0.15 c pin one location 0.10 c 0.08 c c 25 e a 0.10 b c 0.05 c notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm terminal 4. coplanarity applies to the exposed pad as well as the terminals. plane dim min nom max millimeters a 0.800 0.900 1.000 a1 0.000 0.025 0.050 a3 0.200 ref b 0.180 0.250 0.300 d 5.00 bsc d2 2.950 3.100 3.250 e 5.00 bsc e2 e 0.500 bsc k 0.200 --- --- l 0.300 0.400 0.500 2.950 3.100 3.250 *for additional information on our pb-free strategy and soldering details, please download the on semiconductor soldering and mounting t echniques reference manual, solderrm/d. soldering footprint* 0.50 pitch 3.20 0.28 3.20 32 x 28 x 0.63 32 x 5.30 5.30 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, in cluding without limitation special, consequential or incidental damages. typical parameters which may be provided in scillc data sheets and/or specifications can and do vary in different a pplications and actual performance may vary over time. all operating parameters, including typicals must be validated for each customer application by customer's technical e xperts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc prod uct could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney f ees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was neglig ent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800-282-9855 toll free ?usa/canada europe, middle east and africa technical support: ?phone: 421 33 790 2910 japan customer focus center ?phone: 81-3-5773-3850 ncp5391/d the products described herein (ncp5391/d), may be covered by one or more of the following u.s. patent; 7057381. there may be ot her patents pending. pentium is a registered trademark of intel corporation. literature fulfillment : ?literature distribution center for on semiconductor ?p.o. box 5163, denver, colorado 80217 usa ? phone : 303-675-2175 or 800-344-3860 toll free usa/canada ? fax : 303-675-2176 or 800-344-3867 toll free usa/canada ? email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc a sales representative

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